Technical Field
The present disclosure generally relates to FinFETs and, in particular, to lowering contact resistance in a FinFET, while reducing the probability of short circuits between adjacent contacts.
Description of the Related Art
Forming electrical contacts to the terminals of integrated circuit transistors becomes more challenging as the transistors become smaller and more complex. Nanoscale transistor designs such as fin field effect transistors (FinFETs) pose new challenges to circuit designers in positioning adjacent structures that are prone to developing short circuits. Because they tend to be intermittent, short circuits are more likely to cause reliability failures rather than functional test failures. Structures prone to developing short circuits include corners of metal interconnect lines and electrical contacts that are in close proximity to one another, especially when transistor dimensions are at or below 20 nm. To prevent short circuits between contacts, metal lines can be angled or corners can be rounded, for example. Alternatively, short circuit prevention can be provided for some structures by making changes in the fabrication process for conducting features.
Controlling contact resistance poses another challenge to designers of nanoscale circuits. As the contact area shrinks, the associated contact resistance increases according to the relationship R=ρcI/A, wherein A is the contact surface area at the point of contact through which current flows, I is the height of the contact in the direction of current flow, and ρc is the resistivity of the contact metal. Increases in contact resistance significantly degrade overall device performance. Thus, it is important to address and compensate for the increased contact resistance that occurs with each new technology generation by making changes in the transistor design, the contact design, or the transistor fabrication process.